.IDEAS.Controls.OBC.CDL.Logical.Validation.MultiAnd

Information

Validation test for the block IDEAS.Controls.OBC.CDL.Logical.MultiAnd.

The input signals are configured as follows:

• input u₁ has a period of 1 s and a width of 0.5 s.
• input u₂ has a period of 2 s and a width of 0.5 s.
• input u₃ has a period of 3 s and a width of 0.5 s.
• input u₄ has a period of 4 s and a width of 0.5 s.
• input u₅ has a period of 5 s and a width of 0.5 s.

Revisions

• June 28, 2017, by Jianjun Hu:
  First implementation.