BondLib.Electrical.Analog.Spice.Utilities.Qpi

# .BondLib.Electrical.Analog.Spice.Utilities.Qpi

Spice-style PNP transistor model without parasitic resistors and substrate diode

## Information

The PNP element of the Spice bond graph library implements a full-fledges Spice-stye Gummel-Poon model of the PNP bipolar transistor [1-3]. PNPint is a partial model that implements only the internal nodes of the bipolar transistor. The external parasitic resistances, the external capacitor between base and collector, and the substrate are being added from the outside.

    Parameters:

     Level:   Transistor modeling level (default value = 2)
                Level = 1: Ebers-Moll model
                Level = 2: Gummel-Poon model

    DC Model Parameters:

     BF:      Maximum forward current gain at reference temperature (default value = 100)

     BR:      Maximum reverse current gain at reference temperature (default value = 1)

     IS:      Saturation current at reference temperature (default value = 1e-16 Amp)

     ISS:     Saturation current for injection (default value = IS Amp)

     NF:      Forward current emission coefficient (default value = 1)

     NR:      Reverse current emission coefficient (default value = 1)

     GminDC:  Leakage conductance (default value = 1e-19 Mho)

    Low Current Beta Degradation Effect Parameters:

     ISC:     Base-collector leakage saturation current at reference temperature (default value = 0 Amp)

     ISE:     Base-emitter leakage saturation current at reference temperature (default value = 0 Amp)

     NC:      Low-current base-collector leakage emission coefficient (default value = 2)

     NE:      Low-current base-emitter leakage emission coefficient (default value = 1.5)

    Base Width Modulation Parameters:

     VAF:     Forward early voltage (default value = 9e30 Volt)

     VAR:     Reverse early voltage (default value = 9e30 Volt)

    High Current Beta Degradation Effect Parameters:

     IKF:     Corner for forward beta high-current roll-off (default value = 9e30 Amp)

     IKR:     Corner for reverse beta high-current roll-off (default value = 9e30 Amp)

    Junction Capacitor Parameters:

     CJC:     Zero-bias base-collector depletion capacitance at reference temperature (default value = 1e-12 F)

     MJC:     Base-collector junction grading coefficient (default value = 0.33)

     VJC:     Base-collector built-in potential at reference temperature (default value = 0.75 Volt)

     CJE:     Zero-bias base-emitter depletion capacitance at reference temperature (default value = 1e-12 F)

     MJE:     Base-emitter junction grading coefficient (default value = 0.33)

     VJE:     Base-emitter built-in potential at reference temperature (default value = 0.75 Volt)

     XCJC:    Fraction of base-collector depletion capacitance connected to internal base node (default value = 1)

     FC:      Depletion capacitance factor for linearization (default value = 0.5)

    Transit Time Parameters:

     TF:      Ideal forward transit time (default value = 0 sec)

     TR:      Ideal reverse transit time (default value = 0 sec)

    Temperature Compensation and Area Parameters:

     Tnom:    Reference temperature (default value = 300.15 K)

     XTI:     Saturation current temperature exponent (default value = 3)

     XTB:     Forward and reverse beta temperature coefficient (default value = 0)

     EG:      Energy gap for temperature effect on saturation current (default value = 1.11 Volt)

     Area:    Relative area occupied by device (default value = 1)

    Numerical Parameters:

     EMin:    Minimum exponent for linearization of junction current (default value = -100)

     EMax:    Maximum exponent for linearization of junction current (default value = 40)

    Compiler Parameters:

     enforceStates:  State selector (default value = true)
                       enforceStates = true:   Use (external) capacitive voltages as state variables
                       enforceStates = false:  Use (internal) bond graph efforts as state variables

References:

1. Cellier, F.E. (1991), Continuous System Modeling, Springer-Verlag, New York.
2. Hild, D.R. and F.E. Cellier (1994), "Object-oriented electronic circuit modeling using Dymola," Proc. OOS'94, SCS Object Oriented Simulation Conference, Tempe, AZ, pp.68-75.
3. Hild, D.R. (1993), Circuit Modeling in Dymola, MS Thesis, Dept. of Electr. & Comp. Engr., University of Arizona, Tucson.
4. Massobrio, G. and P. Antognetti (1993), Semiconductor Device Modeling with Spice, 2nd edition, McGraw Hill, New York.
5. Schweisguth, M.C. and F.E. Cellier (1999), "A bond graph model of the bipolar junction transistor," Proc. SCS Intl. Conf. on Bond Graph Modeling, San Francisco, CA, pp.344-349.
6. Schweisguth, M.C. (1997), Semiconductor Modeling with Bondgraphs, MS Thesis, Dept. of Electr. & Comp. Engr., University of Arizona, Tucson.

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